1. Field of the Invention
This invention relates to microprocessor design.
2. Related Art
In microprocessors employing pipelined architecture, it is desirable to be in the process of executing as many instructions as possible, so that each element of the pipeline is maintained busy. However, some instructions, such as instructions that load data from external memory or store data into external memory, must generally be executed in their original sequence order, so as to avoid the external memory ever being in an incorrect state. Moreover, when such instructions refer to identical external memory locations, there is no particular need to wait for the actual external memory operations to complete, as the identical data is already available for the processor to operate with.
One problem in the known art is that determining whether two different instructions refer to the identical location in external memory generally requires computing the actual external memory address referenced by each of the two different instructions. This prolongs when the determination can be made, because it requires time (and typically, a pipeline stage) to actually compute the referenced external memory addresses.
Accordingly, it would be advantageous to provide a technique for operating a pipelined microprocessor more quickly, by detecting instructions that load from identical memory locations as were recently stored to, without having to actually compute the referenced external memory addresses. In a preferred embodiment, the microprocessor examines the symbolic structure of instructions as they are encountered, so as to be able to detect identical memory locations by examination of their symbolic structure. For example, instructions that store to and load from an identical offset from an identical register are determined to be referencing the identical memory location, without having to actually compute the complete physical target address.